V-by-One Verification IP
Truechip's V-by-One Verification IP provides an effective & efficient way to verify ASIC/FPGA and SoC components interfacing with the V-by-One HS/HS Plus THine display interface. Truechip's V-by-One VIP is fully compliant with the V-by-One standard. Supports THine V-by-One HS, HS Plus . This lightweight VIP provides an easy plug-and-play interface with minimal impact on design and simulation time.
Key Benefits
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
- Availability of Compliance & Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and coverage points with connectivity examples for all the components
- Consistency of interface, installation, operation, and documentation across all our VIPs
- Provide complete solutions and easy integration in IP and SoC environment
Features
- Fully compliant with V-by-One HS / HS Plus THine Specification.
- Supports V-by-One HS, HS Plus THine Protocol features.
- Supports Full HD, 4K and 8K configurations.
- Supports 18 (HS),24,30,36 (HS and HS Plus) bit color depths.
- Supports up to 32 lanes in HS and up to 64 lanes in HS Plus.
- Supports RGB, YCbCr444,YCbCr422,RGBW,RGBY
- Supports 3 Byte mode, 4 Byte mode, and 5 Byte Mode.
- Supports link rate up to 4Gbps/lane in V-by-One HS and up to 8Gbps/lane in V-by-One HS Plus.
- Supports scalable lane configurations.
- Supports high-speed differential serial interface.
- Supports robust link initialization and synchronization.
- Supports configurable lane rates as per protocol version.
- Supports CDR Lock pattern and ALN Training Pattern.
- Supports protocol framing and encoding verification.
- Supports configurable protocol modes.
- Supports link initialization sequences.
- Supports training and link establishment
- Supports protocol error detection and recovery.
- Supports high-resolution display verification.
- Supports scalable bandwidth verification
- Supports protocol operation across HS, HS Plus
- Supports multiple display resolutions and frame rates.
- Supports interoperability verification
- Supports end-to-end video transport verification
- Supports configurable panel interface verification
- Supports user configurable traffic generation
- Supports complete protocol operation
- Supports callback mechanism for user control
- Supports Dynamic as well as Static Error Injection scenarios.
- Strong Protocol Monitor with real time exhaustive, programmable checks.
- On-the-fly protocol checking using protocol check functions, static and dynamic assertions.
- Built-in coverage analysis Graphical analyzer to show transactions for easy debugging.
Deliverables
- V-by-One BFM's for
- Transmitter Link Layer
- Receiver Link Layer
- Transmitter - Serializer (TX PHY)
- Receiver –Deserializer (RX PHY)
- Availability of Compliance & Regression Test Suites
- Layered Monitor and Scoreboard.
- Test Environment and Test Suite:
- Basic and Directed Protocol Tests.
- Random Tests.
- Error Scenario Tests.
- Assertions & Cover Point Tests.
- Compliance Test Suite.
- User Test Suite.
- Integration guide, user manual, and release notes
- GUI analyzer to view simulation packet flow
